Great Lakes Semiconductor Launches Modular Fab and Packaging Project

semiconductor-digest.com Oct 16, 2026

Great Lakes Semiconductor Launches Modular Fab and Packaging Project

Curated by Shubham · TechCapsules · Oct 16, 2026

AI-summarised brief · reviewed before publication

Great Lakes Semiconductor (GLS) unveiled its first project on the Great American ChipForge platform, part of the company’s Innovation Funnel initiative. The effort integrates GLS design centers, modular wafer fabrication, and FINPAT packaging and test, targeting AI‑enabled vehicle sensors. Partners include Neitas, Daikin, BlueDot Ventures, FMC, Altascient, and APES, who will supply modular fab equipment, low‑energy sensors, ferroelectric memory, predictive planning, and additive packaging substrates. The project demonstrates GLS’s distributed, end‑to‑end integration capability and aims to accelerate time‑to‑market for new automotive sensor products.

💡 Why It Matters

· By combining modular fabrication with additive packaging, GLS can rapidly prototype and scale niche sensor technologies, potentially shortening the development cycle for automotive AI components.
· This approach may set a new standard for flexible, ecosystem‑driven semiconductor production.

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Advantest Readies Silicon Photonics Test for Volume Production

Advantest has launched the first electro‑optical test cell designed for high‑volume silicon‑photonic IC production, partnering with FormFactor to integrate optical probers into its V93000 platform. The system, called TRITON, combines a TEL production prober with fiber‑alignment capabilities and a new SmarTest software suite that controls lasers, polarization controllers, attenuators, power meters and optical spectrum analyzers housed in a turnkey rack built in San Jose. The rack, TÜV‑certified and equipped with safety interlocks for Class 3B lasers, is already installed at major foundries such as TSMC, Tower, GlobalFoundries, STMicroelectronics and Samsung. Advantest has patented a calibration method to equalize power at each fiber tip, supporting devices with up to 40 fibers and preparing for future chips with over 100 fibers and parallel testing of multiple devices.

💡 By delivering a ready‑to‑use, scalable testing solution, Advantest removes a critical bottleneck, letting silicon‑photonic chip makers focus on design rather than building complex test infrastructure.

androidcentral.com · Oct 16

Jury finds Arm guilty in licensing breach, Qualcomm awarded just $2 in…

A Delaware jury ruled that Arm breached a licensing agreement with Qualcomm and interfered with its business relationships, awarding Qualcomm $1 in damages per offense, totaling $2. The case stemmed from Qualcomm’s claims that Arm, after acquiring Nuvia in 2021, withheld chip‑testing tools and threatened to terminate a key license, allegedly damaging a $170 million deal with Meta. Arm denied the allegations, asserting it acted in good faith. The verdict may lead to further litigation over royalty payments and future licensing terms.

💡 The ruling underscores the fragility of chip‑design partnerships and could reshape how major manufacturers negotiate royalty structures, potentially affecting the cost and availability of next‑generation mobile processors.

semiconductor-digest.com · Oct 16

ABM Maps the Six Phases of a Fab’s Life

ABM completed its acquisition of WGNSTAR, a fab‑services firm, earlier this year, integrating WGNSTAR’s strong operational focus with ABM’s construction and facilities expertise. The combined entity now covers the full semiconductor fab life cycle, broken into six phases—construction, fit‑out, equipment install, full operations, upgrades, and decommissioning—grouped under build, run, and evolve. ABM’s workforce of 140,000, largely in the U.S., will leverage cross‑training to elevate employees from construction roles to higher‑value technical positions, positioning the company to capitalize on the projected U.S. fab boom.

💡 The deal consolidates critical end‑to‑end services, enabling faster, more integrated fab deployment and upgrades, which is essential as U.S. fabs expand to meet global demand.

semiconductor-digest.com · Oct 16

Nordson SonoFlex Wins 2026 Best of West Award at SEMICON West

Nordson Test & Inspection’s SonoFlex Acoustic System earned SEMI and Semiconductor Digest’s Best of West award at SEMICON West 2026. The accolade recognizes products that markedly advance electronics manufacturing. SonoFlex is an automated inspection tool that scans small panel‑based assemblies twice as fast as legacy equipment, thanks to Nordson’s advanced pulser and transducer technology. It operates across the broadest frequency range yet seen in production, and its new FlexCore software, paired with Nordson Intelligence AI Multi Gate Image Analysis, pinpoints defects and isolates true void counts. The system’s modular architecture permits up to four units to work together, boosting throughput by up to eight times. The award was presented at Nordson’s booth on the day of the show for industry recognition.

💡 By slashing inspection time while expanding defect detection capability, SonoFlex lets fabs accelerate production cycles without sacrificing yield, a rare combination in the race to scale advanced packaging.

semiconductor-digest.com · Oct 15

VON ARDENNE Scales HiPIMS Sputtering from Wafers to Panels

VON ARDENNE, a Dresden‑based PVD specialist, announced at SEMICON West that its HISS horizontal inline platform will use high‑power impulse magnetron sputtering (HiPIMS) to deposit barrier and seed layers in through‑glass vias (TGVs) on panel‑level semiconductor substrates. The company’s tools accommodate panels up to 650 × 650 mm and operate inline, reducing vacuum breaks and handling risk. By pulsing plasma, HiPIMS improves ion bombardment for conformal coating, offering a cost‑effective alternative to ALD for high‑aspect‑ratio vias. The firm collaborates with glass suppliers and via‑drilling partners to optimize sidewall formation and adhesion layers.

💡 The move enables scalable, high‑throughput panel processing, a critical step as semiconductor devices shift toward larger, panel‑level form factors. It also positions VON ARDENNE to support future optical interposers, expanding the company’s role beyond traditional metal deposition.

nextplatform.com · Oct 15

A Decade In, zeroRISC Sees A Bright Future For Open Silicon

ZeroRISC, founded by former Google OpenTitan lead Dominic Rizzo, is accelerating commercial adoption of open silicon root‑of‑trust (RoT) designs. In May, the startup partnered with Qualcomm, Analog Devices, Meta, and the Max Planck Institute to launch Pavona under GlobalPlatform, a neutral ecosystem for building secure hardware. Pavona offers a production‑ready post‑quantum cryptography stack and a composable platform for RoT and chip subsystems, mirroring open‑source software projects. The initiative builds on RISC‑V’s maturity and the semiconductor industry’s shift toward modular IP reuse, aiming to reduce costs, enhance transparency, and speed innovation.

💡 By providing a standardized, open framework for secure silicon, Pavona could lower entry barriers for startups and accelerate the deployment of resilient hardware across data centers and edge devices.