Laser Slicing of Large-Area Diamond Substrates

semiconductor-digest.com Nov 2, 2026

Laser Slicing of Large-Area Diamond Substrates

Curated by Shubham · TechCapsules · Nov 2, 2026

AI-summarised brief · reviewed before publication

Researchers at Chiba University have demonstrated a laser‑based method for slicing diamond substrates. The team compared one high‑pressure high‑temperature (HPHT) diamond and two chemical vapor deposition (CVD) diamonds with varying nitrogen levels, exposing them to ultrashort laser pulses from 233 fs to 30 ps. CVD samples responded to shorter pulses, producing either isolated marks or continuous modified zones, while the HPHT crystal required longer pulses and showed more stable modifications. Using 10 ps pulses, the authors created a grid of modifications in an 8 mm × 8 mm CVD diamond and, after steps, split the wafer along the {100} plane. The slice is 710 times larger than the 300 µm‑square HPHT piece previously achieved, marking a step toward industrial‑scale diamond substrates for optics, heat spreaders and power electronics.

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TechInsights Identifies Five Trends Reshaping the Semiconductor Market

TechInsights released its 2027 Outlook Report, outlining five forces that will dominate the semiconductor sector next year. The analysis flags memory as the primary bottleneck, projecting $1.6 trillion in memory revenue and a total market size of $2.6 trillion, with memory comprising 62 % of sales—up from roughly a quarter historically. AI‑driven demand for high‑bandwidth memory (HBM) has already booked 2027 capacity, diverting resources from NAND and other categories and pressuring chip architectures, manufacturing investment, and product roadmaps. Advanced packaging will face similar strain as chiplet designs and HBM compete for limited CoWoS and SoIC capacity. AI’s shift toward inference fuels custom silicon and silicon‑photonic transceivers, while manufacturing emissions are forecast to hit a record 197 million metric tons CO₂e. Rising memory costs could split consumer electronics into premium and cost‑constrained tiers.

💡 Memory scarcity will force designers to re‑engineer products, reshaping the competitive landscape across AI, automotive and consumer markets.

nextplatform.com · Nov 2

Qualcomm Has Eyes On The AI Inference Datacenter With HBC And AI250

Qualcomm unveiled its high‑bandwidth computing (HBC) architecture and the AI250 inference platform, targeting the datacenter AI‑inference market. HBC moves compute dies next to a stacked LPDDR memory stack, eliminating the “memory wall” that limits performance as models grow larger. By shortening data travel from millimeters to micrometers, the design promises higher bandwidth, lower latency, and significant energy savings compared with traditional DDR or HBM‑based solutions, which incur higher cost and power consumption. The first‑generation HBC pairs the LPDDR stack with a dedicated AI accelerator, while some tasks can offload to Qualcomm’s Dragonfly‑based AI250 system‑on‑chip. Production of the AI250 has begun, with broader release slated for later this year.

💡 By collapsing the distance between memory and compute, Qualcomm’s HBC could redefine cost‑per‑inference metrics, giving datacenters a more power‑efficient path to scale agentic AI workloads.

quantumcomputingreport.com · Oct 31

Wolfspeed Commercializes Transparent Silicon Carbide Substrates for Quantum Computing and Integrated Photonics

Wolfspeed Inc. has launched commercial optical‑grade transparent silicon carbide (TSiC™) wafers, offering 150 mm and 200 mm substrates with 300 mm samples. The single‑crystal 4H‑SiC material targets quantum computing, integrated photonics, and cryogenic packaging, providing a scalable platform for solid‑state spin qubits and low‑loss photonic circuits. With optical absorption ≤ 0.05 cm⁻¹ across visible wavelengths, high refractive index, and excellent thermal conductivity, the wafers enable monolithic integration of spin defects, waveguides, and photon routing. The availability addresses long‑standing wafer‑scale bottlenecks that limited wide‑bandgap quantum devices and positions SiC as a viable alternative to diamond for large‑area quantum hardware.

💡 By delivering wafer‑scale, optical‑grade SiC, Wolfspeed removes a critical fabrication hurdle, allowing quantum developers to mass‑produce spin‑photon nodes with standard semiconductor tools. This shift could accelerate the transition from laboratory prototypes to commercially viable quantum processors.

quantumcomputingreport.com · Oct 31

IP Law Firm MBHB Launches Dedicated Quantum, Optics, and Semiconductors Practice Group…

Intellectual property firm McDonnell Boehnen Hulbert & Berghoff LLP (MBHB) has launched a dedicated Quantum, Optics, and Semiconductors Practice Group in Chicago. The new team will advise hardware developers, research universities, and government contractors as the Illinois Quantum and Microelectronics Park (IQMP) expands, with anchor tenants like PsiQuantum and IBM deploying commercial quantum infrastructure. The practice focuses on patent eligibility under 35 U.S.C. § 101, emphasizing physical apparatus claims over abstract algorithms, and addresses federal march‑in rights and export controls tied to public funding.

💡 By aligning legal expertise with the region’s quantum‑hardware boom, MBHB positions itself to shape how emerging technologies secure intellectual property and navigate complex regulatory landscapes.

nextplatform.com · Oct 31

AI Arms Race Puts Sovereign Supply Chains in the Spotlight

South Korea is intensifying its push for a sovereign AI hardware ecosystem, leveraging domestic memory giants SK Hynix and Samsung and nearby fabs such as TSMC and Rapidus. Two home‑grown startups, Rebellions and FuriosaAI, have already shipped silicon—Rebellions’ Rebel100 matches Nvidia’s three‑year‑old H200, while Furiosa’s RNGD delivers 2.25 × the performance‑per‑watt of an older A100. This week Furiosa announced a $620 million Series D round to scale RNGD production to about 20,000 units this year and double output by 2027, with Samsung and LG as key customers. The next‑gen accelerator will be fabricated on a 2 nm process, use a multi‑die chiplet design, and incorporate HBM4/4e, developed alongside Broadcom’s advanced packaging technology. The effort reflects broader geopolitical concerns about reliance on U.S. GPU supply and mirrors similar sovereign AI drives in Japan and Europe.

💡 Securing a domestically produced AI accelerator shields South Korea from abrupt export bans and positions it as a strategic hardware hub in a tightening global tech rivalry.

nextplatform.com · Oct 29

How to Evaluate CPU Performance for Agentic AI

The CPU, once eclipsed by GPUs and XPUs for AI workloads, is re‑emerging as the linchpin for agentic AI, prompting analysts to project market growth from $26 billion in 2025 to $246 billion by 2031, driven largely by AI‑host CPUs and sandbox processors. Evaluating these chips now requires a multi‑level approach—socket, system, and rack—focusing on single‑thread speed, core scaling, and power‑thermal limits to support concurrent AI agents under strict SLAs. Arm’s Jeff Defilippi stresses that traditional benchmarks (e.g., TPC‑E, InferenceX, TPCx‑AI) remain useful for component analysis but must be integrated with end‑to‑end task metrics that capture the dynamic chaining of model calls, retrieval, code execution, and state changes characteristic of agentic workflows. The proposed methodology blends established tests with holistic workload measurements to guide purchasing decisions across hyperscalers, cloud builders, and enterprises.

💡 It offers a concrete framework for matching CPU capabilities to the intricate, real‑time demands of autonomous AI agents, preventing costly mismatches in rapidly expanding data‑center deployments.