AI’s Next Power Challenge Is Inside the Delivery Path

semiconductor-digest.com Jun 19, 2026

AI’s Next Power Challenge Is Inside the Delivery Path

Curated by Shubham · TechCapsules · Jun 19, 2026

AI-summarised brief · reviewed before publication

The semiconductor industry faces a critical challenge in power delivery to AI systems, with traditional lateral power architectures resulting in 15-20% power loss due to resistive losses. As device power levels climb and operating voltages drop, the industry is shifting towards vertical power delivery schemes to reduce losses and improve efficiency. Technologies like Saras Micro Devices' STILE platform embed passive functionality into system PCB and package structures, supporting voltage regulation demands and freeing board-level real estate. This shift is redefining packaging discussions, with packaging becoming part of the power architecture. The industry must evaluate energy efficiency through the lens of power delivery path efficiency, not just processor performance and thermal management, to optimize compute capabilities.

💡 Why It Matters

· Every watt lost in the power delivery path is a watt unavailable for compute, directly impacting AI system performance.
· Vertical power delivery schemes can significantly reduce energy waste and infrastructure strain.

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