Ashwini Vaishnaw lays out six pillars of Semicon 2.0, from chip design to clean room talent

yourstory.com Sep 17, 2026

Ashwini Vaishnaw lays out six pillars of Semicon 2.0, from chip design to clean room talent

Curated by Shubham · TechCapsules · Sep 17, 2026

AI-summarised brief · reviewed before publication

Union Minister Ashwini Vaishnaw outlined the six pillars of “Semicon 2.0,” the second phase of India’s semiconductor programme, at the opening of Semicon India 2026 in New Delhi on September 17. He said the first phase, funded at about $8 billion, established a base with 12 approved projects and five operational fabs, including Micron’s plant in Surat. The new phase, earmarked for up to $13.5 billion, will expand the ecosystem across design, machines and materials, fab capacity, advanced packaging, applied R&D, and clean‑room talent. Targets include at least 200 chip‑design startups, a $5 billion equipment commitment from Applied Materials, a 3D‑packaging unit in Odisha, and training 100,000 technicians, while over 400 universities now host EDA tools.

💡 Why It Matters

· By shifting focus from isolated fabs to a full supply‑chain ecosystem, India aims to accelerate self‑reliance and create a multiplier effect that could position the country as a global semiconductor hub.

Capsules Semiconductors

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Microsoft Discovery lowers barriers to chip design

Microsoft Discovery, the company’s new AI‑driven chip‑design platform, enabled a former aerospace engineer to take a RISC‑V core and a small AI accelerator from specification through logical C, high‑level synthesis, RTL and finally physical layout using the open‑source OpenROAD flow and SKY130 process node. The author documented the end‑to‑end workflow on GitHub and demonstrated the tool’s ability to lower the expertise barrier for non‑silicon specialists. The project, presented at DAC 2026, also showcased how AI assistance can streamline both design and optimization stages, allowing participants to focus on architecture rather than low‑level implementation details. Microsoft Discovery thus provides a guided, open‑source path for learning and prototyping chips without requiring access to advanced foundry resources.

💡 By democratizing the chip‑design workflow, Microsoft Discovery turns a traditionally niche skill into a teachable, reproducible process, accelerating talent development and fostering open‑hardware innovation.

newindianexpress.com · Sep 17

Micron to assemble “hundreds of millions” of memory chips at Sanand, Gujarat…

Micron Technology announced at SEMICON India 2026 that its Sanand plant in Gujarat will assemble and test hundreds of millions of DRAM and NAND memory chips in 2025, after already producing tens of millions this year. The facility, India’s first semiconductor assembly‑test site and the inaugural project under the India Semiconductor Mission, began production earlier in 2024 and now ships finished products worldwide. CEO Sanjay Mehrotra highlighted that the plant’s current capacity exceeds the entire Indian laptop market’s memory needs and that the expansion supports the surge in artificial‑intelligence workloads. Micron employs more than 7,000 staff in India, with engineering centres in Hyderabad and Bengaluru contributing over 3,700 patents, and runs university collaborations and STEM programmes to develop local talent.

💡 The scale‑up turns India from a design hub into a genuine memory‑chip supplier, giving AI‑driven firms a domestic source for critical data‑storage components.

teslarati.com · Sep 17

Tesla and SpaceX take “Terafab” Trademark fight to Federal Court

Tesla and SpaceX have asked a federal judge in Austin to declare that their planned “Terafab” semiconductor fab does not infringe a trademark held by Illinois nanotech firm TERA‑print LLC. The dispute began after Tesla filed three trademark applications for “Terafab” and “Tesla Terafab” on May 18, prompting TERA‑print to send a cease‑and‑desist letter and expand its own registration to include semiconductor materials on May 22. Negotiations between the parties collapsed after six meetings from June to August, leading the aerospace and auto companies to seek a declaratory judgment in the Western District of Texas. TERA‑print, which supplies desktop photolithography printers and holds a Defense Department contract, says it will vigorously defend its mark and protect its growing market presence.

💡 Control of the “Terafab” name will determine whether Tesla and SpaceX can brand their $16.8 billion chip complex without legal encumbrances, shaping the identity of a facility poised to supply AI hardware for both companies.

newindianexpress.com · Sep 17

Micron to assemble “hundreds of millions” of memory chips at Sanand, Gujarat…

Micron Technology announced at SEMICON India 2026 that its Sanand plant in Gujarat will assemble and test hundreds of millions of DRAM and NAND memory chips in 2025, after already producing tens of millions this year. The facility, India’s first semiconductor assembly‑and‑test (A&T) line and inaugural project under the India Semiconductor Mission, began commercial production earlier in 2024 and now ships finished products worldwide. CEO Sanjay Mehrotra highlighted that Micron’s current capacity exceeds the entire Indian laptop market’s demand and that expansion supports AI‑driven surge in memory needs. Micron employs more than 7,000 staff, backs tens of thousands of supply‑chain jobs, and engineering centres have contributed 3,700 patents. The company also deepens ties through university collaborations and its Micron Foundation.

💡 By moving from prototype to high‑volume assembly, India is transitioning into a genuine export hub for memory chips, reducing reliance on overseas fabs and strengthening its role in the AI data supply chain.

iam-media.com · Sep 17

Alibaba, NXP, Renesas among patent sellers in August US transactions

In August, a series of U.S. patent transactions featured major technology firms Alibaba Group, NXP Semiconductors and Renesas Electronics as sellers, alongside a range of smaller entities. The deals, many of which were acquired by non‑practicing entities (NPEs), covered a spectrum of intellectual property including semiconductor timing technologies, AI‑enabled video and image‑processing algorithms, and other specialized assets. The filings, recorded with the United States Patent and Trademark Office, illustrate a continued trend of high‑value IP being monetized through secondary markets rather than direct product development. Analysts note that the involvement of prominent Asian manufacturers underscores the global reach of the U.S. patent marketplace and the strategic importance of securing licensing rights for emerging AI and semiconductor innovations.

💡 The transaction mix shows that leading chip makers are actively liquidating core AI and timing patents, reshaping who controls critical technology standards in the U.S. market.

semiconductor-digest.com · Sep 17

Ireland’s Emergence as a Full-Stack Semiconductor Powerhouse

Ireland has developed a comprehensive semiconductor ecosystem over five decades, now highlighted by a 2040 national strategy that consolidates EDA/IP, design, fabrication, and advanced packaging within a single cluster anchored by Analog Devices. The country participates in the European Chips Act, co‑investing in three pan‑European pilot lines for sub‑2‑nanometer chips, fully depleted silicon‑on‑insulator, photonics, and advanced packaging. A new coordinating research institute, Tyndall National Institute, and a €100 million government fund aim to support future manufacturing infrastructure. Talent acquisition remains the critical challenge, with AI chip firms already present and a university pipeline being mapped to meet future needs.

💡 Ireland’s integrated semiconductor strategy positions it as a pivotal player in Europe’s high‑tech supply chain, potentially reshaping regional manufacturing and innovation dynamics.