Conference Report: System Level Thinking Needed in AI Era
AI-summarised brief · reviewed before publication
At the 2026 Symposium on VLSI Technology and Circuits, OpenAI hardware chief Richard Ho urged a shift from isolated transistor optimization to system‑level co‑optimization of compute, memory, and interconnects. IBM’s Dechao Guo projected a transition to gate‑all‑around and stacked CFETs beyond 1 nm, while TSMC’s L.C. Lu highlighted CoWoS scaling and a 34‑fold HBM bandwidth increase. Micron’s Nirmal Ramaswamy announced sub‑50 nm wafer‑to‑wafer overlay for DRAM stacking, and SK hynix noted data centers consume 70% of global DRAM output, signaling potential long‑term supply strain.
💡 Why It Matters
- · The conference underscores that future semiconductor performance hinges on integrated system design, not isolated scaling.
- · This pivot could reshape manufacturing priorities and accelerate AI‑driven hardware innovation.