Enabling Next-Generation Plasma Dicing with Ultrasonic Spray Coating and Digital Lithography

semiconductor-digest.com Oct 28, 2026

Enabling Next-Generation Plasma Dicing with Ultrasonic Spray Coating and Digital Lithography

Curated by Shubham · TechCapsules · Oct 28, 2026

AI-summarised brief · reviewed before publication

EV Group researchers demonstrated that ultrasonic spray coating can apply a conformal, photo‑sensitive resist over complex bump, pillar, and cavity topographies on 200 mm and 300 mm wafers. Combined with EVG’s LITHOSCALE maskless digital lithography, the process yields narrow dicing streets (as small as 5 µm) with steep sidewalls and clean edges, eliminating the laser step required by water‑soluble coatings. The technique reduces mechanical stress, avoids contamination from film frames and tape, and scales to thinner dies and finer pitches.

💡 Why It Matters

· By removing the need for laser exposure and film‑frame handling, the method streamlines plasma dicing for advanced packaging, enabling higher throughput and lower defect rates in next‑generation semiconductor devices.

Capsules Semiconductors

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Flexell Space and Satoro Agree to Collaborate on In-Orbit Demonstration of Next-Generation…

Flexell Space and Singapore‑based Satoro have signed an agreement to demonstrate Flexell’s next‑generation CIGS and perovskite solar cells on two CubeSat missions launched aboard SpaceX Falcon 9 rockets in 2027 and 2028. Satoro will build the satellites, while Flexell will supply the solar cells and test modules for integration. The missions aim to validate the cells’ power output, radiation tolerance and long‑term reliability in the space environment, comparing in‑orbit data with previous ground‑test results from Flexell’s 2025 and 2026 KSLV‑II flights. Collected data will inform design refinements and provide the technical evidence required for global customers, moving the technology toward commercial supply for satellites and other space infrastructure.

💡 Demonstrating ultralight, high‑efficiency solar cells in orbit will prove a viable, low‑cost power source for the growing CubeSat market, accelerating the shift to more capable, affordable satellite constellations.

semiconductor-digest.com · Oct 28

From Lab to Fab: The Rise of HiPIMS in Semiconductor Manufacturing

High‑power impulse magnetron sputtering (HiPIMS) is being transitioned from laboratory research to high‑volume semiconductor fab lines, according to a VON ARDENNE technical paper. The authors detail the engineering upgrades required to scale the process to 200 mm‑plus wafers, emphasizing real‑time voltage‑current pulse monitoring, low‑inductance feed lines, programmable pulse shaping, rapid arc suppression and advanced target cooling. Synchronized substrate biasing is highlighted as a means to accelerate ions during peak flux, yielding denser, better‑adhering films with superior step coverage. A key use case is through‑glass via (TGV) metallization for advanced packaging, where HiPIMS enables partially ion‑controlled deposition of titanium adhesion layers and copper seed films. The paper proposes a two‑ to four‑year roadmap from pilot retrofits to validated production, treating scale‑up as a comprehensive system‑engineering effort.

💡 By turning sputtering into a controllable ion‑driven process, HiPIMS can unlock tighter device geometries and more reliable interconnects in next‑generation packaging.

9to5google.com · Oct 28

RAMageddon is ready to rage on through 2030

SK Hynix announced on its earnings call that its DRAM and high‑bandwidth memory (HBM) production is fully booked through 2029, extending the global “RAMageddon” shortage for at least three more years. The company’s chief financial officer said demand growth outpaces supply, and the lead times required to build new fabs mean capacity constraints will persist into 2030. SK Hynix has already secured long‑term contracts covering more than half of its 2027‑2028 capacity, but still cannot meet all customer volume needs. Competitor Micron warned that 2027 will be tighter than 2026, while Samsung, the market leader, faces similar supply‑demand imbalances. Industry analysts note that expanding production infrastructure is a lengthy process, leaving the shortage unabated.

💡 The prolonged scarcity forces OEMs to redesign products or absorb higher component costs, reshaping pricing and launch strategies across the tech sector.

semiconductor-digest.com · Oct 28

How to Tackle Hidden Production Risks in Semiconductor Operations

Kelly Fabs’ business process outsourcing partners use failure mode and effects analysis (FMEA) to identify and mitigate hidden risks in manual semiconductor operations such as wafer lot packaging, reticle transport, preventive maintenance, and parts cleaning. In a recent assessment, the team scored each step for severity and probability, then implemented a new bagging system, ergonomic improvements, structured technician rotation, and updated checklists. A subsequent rescore showed a reduction in high‑risk steps, demonstrating the method’s scalability across sites and its integration with 8D incident reviews.

💡 By systematically quantifying manual process hazards, Kelly Fabs can proactively reduce costly downtime and protect the integrity of high‑value materials, a critical advantage as CHIPS Act‑backed capacity expands.

semiconductor-digest.com · Oct 28

Why SiC and GaN Need Their Own Qualification Standards

Silicon carbide (SiC) and gallium nitride (GaN) power devices are rapidly entering electric‑vehicle inverters, onboard chargers, solar inverters and data‑center supplies, but the industry still relies on qualification standards—JEDEC JESD47, AEC‑Q101 and JESD22 stress tests—originally devised for silicon. Dr. Pradyumna Gupta of Infinita Lab explains that wide‑bandgap materials exhibit distinct failure mechanisms: SiC basal‑plane dislocations can evolve into stacking faults that cause bipolar degradation, while its gate‑oxide traps and breakdown behavior diverge from silicon models. GaN suffers from charge‑trapping‑induced dynamic on‑resistance shifts (current collapse) and dielectric‑trap‑driven threshold instability. Test conditions also fall short; for example, high‑temperature reverse‑bias testing often uses only 80 % of a device’s rated voltage, leaving many labs applying lower stress. Consequently, published qualification data may appear robust yet fail to predict real‑world degradation, posing a central challenge as power electronics push toward higher voltages, temperatures and frequencies.

💡 Without standards that reflect SiC and GaN’s unique failure modes, manufacturers risk deploying components that under‑perform in critical applications, jeopardizing reliability and safety.

semiconductor-digest.com · Oct 28

The Measurement Gap: Why Metrology and Inspection Is Outgrowing the Industry’s Ability…

Wafer‑fab equipment spending is projected to reach $162 billion in 2026, a 25 % rise, with metrology and inspection tools comprising 14 % of the market. Yole Group’s analyst Clara Grcevic says the segment’s 2031 forecast has been lifted from $24.7 billion to $31.4 billion, driven chiefly by memory‑chip demand spurred by artificial‑intelligence workloads. Unlike lithography, metrology and inspection lack a single scaling axis, so resolution and throughput cannot improve together. Supplier lead times have lengthened 1.5‑ to 2‑fold, and emerging structures—hybrid‑bonded interfaces, EUV stochastic effects, panel‑level packaging, and glass‑core substrates—outpace tools. Grcevic identifies two coping strategies: a wave of suppliers backed by chipmakers and equipment makers, and hybrid metrology that fuses measurement techniques and data analytics. Both mitigate shortfall, yet gap persists wherever throughput remains bottleneck.

💡 The widening capability gap threatens to throttle production yields as advanced node designs become increasingly complex.