Intel CEO Lip-Bu Tan on the one thing troubling his customers the most: I think in terms of the AI, the biggest challenge is...

timesofindia.indiatimes.com Sep 21, 2026

Intel CEO Lip-Bu Tan on the one thing troubling his customers the most: I think in terms of the AI, the biggest challenge is…

Curated by Shubham · TechCapsules · Sep 21, 2026

AI-summarised brief · reviewed before publication

Intel CEO Lip‑Bu Tan warned that memory scarcity is now the primary obstacle for companies building AI infrastructure, citing a five‑to‑seven‑fold rise in memory prices and limited production that forces project delays. Speaking at Splunk’s .conf26 in Denver, Tan explained that demand for high‑bandwidth memory (HBM) from Nvidia and AMD accelerators has outstripped the output of Samsung, SK hynix and Micron, prompting a shift of existing lines to HBM and reducing capacity for standard DRAM. He relayed industry forecasts that relief won’t arrive until 2028. Tan also noted CPU shortages, with Intel able to meet only half of customer orders, and highlighted the geopolitical risk of relying on Taiwanese packaging suppliers, which dominate 95% of the market. Intel’s 18A node is now in mass production, with 14A slated to start soon.

💡 Why It Matters

· The bottleneck forces AI developers to postpone deployments, throttling the rollout of next‑generation services that rely on massive model inference and orchestration.

Capsules Semiconductors

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SEALSQ, WISeKey, and Canton of Jura Execute MoU for CHF 40–60M ($48.7M–$73M…

SEALSQ Corp, its parent WISeKey International Holding Ltd, and the Swiss Canton of Jura signed a Memorandum of Understanding to create the Jura Post‑Quantum Semiconductor and Cybersecurity Center. The public‑private partnership will invest CHF 40 million to CHF 60 million over six years to develop regional expertise in personalizing, testing, and certifying hardware‑embedded post‑quantum cryptography. The center will use SEALSQ’s QS7001 Quantum Shield microcontrollers, which run NIST‑standard ML‑KEM and ML‑DSA lattice algorithms, and will support defense, aerospace, and critical infrastructure sectors. The facility aims to create 250+ jobs by year eight, with over 60 % of positions held by local residents.

💡 By anchoring advanced post‑quantum hardware development in Switzerland, the project strengthens national cybersecurity resilience and positions the region as a hub for secure microelectronics, directly supporting defense and critical infrastructure needs.

semiconductor-digest.com · Sep 21

Taming Heat at the Nanoscale to Satiate Energy-Hungry Artificial Intelligence

Korean University researchers have engineered a “double‑confined” phase‑change memory cell that layers antimony telluride with nickel ditelluride and molybdenum ditelluride. The design confines heat to specific regions, allowing two distinct data states to be written sequentially without disturbing the underlying material. This architecture reduces reset energy by up to 76 % to 115 pJ, speeds switching to 50 ns, and extends endurance beyond one million cycles. The thin layers can be deposited with existing sputtering equipment, making the technology scalable for data‑center chips.

💡 By slashing power and heat in memory cells, the new design directly tackles the energy bottleneck that limits AI workloads. It offers a manufacturable path to denser, cooler, and more reliable memory for tomorrow’s high‑performance computing.

electronicsweekly.com · Sep 21

Nordic nRF54LC10A SoC expands nRF54L series for cost-sensitive IoT

Nordic Semiconductor unveiled the nRF54LC10A system‑on‑chip, targeting ultra‑low‑cost tags, trackers and smart‑home sensors. The device integrates Bluetooth LE, Bluetooth Channel Sounding, Thread, Zigbee and Matter, and offers the same security and software ecosystem as the higher‑end nRF54L series. It is built around a 128 MHz Arm Cortex‑M33 core with a RISC‑V co‑processor, 1 MB non‑volatile memory, 192 KB RAM, three SPI/TWI/UART interfaces and an ADC. Radio performance includes 4.0 mA receive and 5.8 mA transmit currents at 0 dBm, +4 dBm peak output, –97 dBm Bluetooth LE sensitivity and –101 dBm 802.15.4 sensitivity, with sleep currents between 0.5 µA and 1.6 µA. The chip is offered in two 1.9 × 2.3 mm CSPs and a QFN package, is available for sampling now, and will enter production in Q2 2027 with development kits due Q1 2027.

💡 By delivering full‑stack connectivity and security in a footprint and price tier previously limited to single‑protocol chips, the nRF54LC10A enables developers to launch truly multi‑standard IoT products without compromising on battery life or feature set.

aryanage.com · Sep 21

India’s Semiconductor Push Gains Momentum as SEMICON 2026 Draws Global Industry

India’s semiconductor sector received a major boost at SEMICON India 2026, inaugurated by Prime Minister Narendra Modi in New Delhi. The three‑day showcase at Yashobhoomi attracted over 40,000 visitors, 400 executives, 150 speakers and 600 companies from 52 nations. More than 50 memoranda of understanding were signed, underpinning the government’s Rs 1,27,500 crore (≈ USD 15 billion) budget for the “Semicon 2.0” roadmap, which focuses on design, fab construction, ATMP/OSAT capacity, equipment, R&D and talent development. Union Minister Ashwini Vaishnaw announced investment pledges totalling roughly Rs 1 lakh crore (USD 11‑12 billion). The event signals India’s intent to embed itself in global chip supply chains and accelerate the transition from design‑only to full‑stack silicon‑to‑systems production.

💡 By consolidating unprecedented foreign capital and expertise, India is positioning itself to reduce reliance on overseas chip sources and become a pivotal node in the worldwide semiconductor network.

brandiconimage.com · Sep 21

Taiwan Steps Up Chip Race With New Advanced Packaging Park

Taiwan inaugurated an advanced‑packaging industrial park in Kaohsiung on Monday, marking a major expansion of its semiconductor ecosystem. The Baipu Industrial Park, spanning about 88.7 hectares, will host two TSMC facilities: a technology‑validation laboratory and a talent‑training centre, slated to start operations in Q4 2029. Deputy Mayor Lo Ta‑sheng said the site will enable equipment and material suppliers to conduct research alongside TSMC’s packaging lines. President Lai Ching‑te highlighted the strategic role of advanced packaging in AI and high‑performance computing, noting the park could accelerate the transition from testing to mass production. The cluster aims to integrate supply‑chain partners, strengthen Taiwan’s position in global chip competition, and support AI‑chip designers such as Nvidia, AMD and Broadcom for future technology roadmaps globally.

💡 Consolidating validation and talent development with suppliers shortens AI‑chip rollout cycles, giving Taiwan’s fabs a decisive timing advantage over competitors.

gyanhigyan.com · Sep 21

Assam’s Semiconductor Facility Nears Operational Launch

Assam is on the cusp of launching its Tata Electronics semiconductor OSAT plant in Jagiroad, with trial runs now at roughly 25 % of capacity and commercial production slated for December‑January. The 592‑acre facility represents a ₹27,000 crore investment and is designed to output up to 48 million chips per day using advanced flip‑chip and ISIP packaging. Initial output will serve automotive, electric‑vehicle, telecom and consumer‑electronics sectors, while full‑scale capacity and a stable supply chain are expected to mature over the next one to two years. The project anticipates creating about 27,000 direct and indirect jobs, including a growing cohort of women technicians, and is supported by state infrastructure upgrades such as water, power and housing.

💡 The plant positions Assam as a rare Indian hub capable of high‑volume, advanced‑packaging chip production, reducing the country’s reliance on imported semiconductors.