NIT Warangal scholar develops power chip that could boost battery life in smart gadgets
AI-summarised brief · reviewed before publication
A PhD scholar at the National Institute of Technology Warangal, Kaira Anupama, has created a new Power Management integrated circuit designed to extend battery life in Internet‑of‑Things devices. The chip, developed over three years with a research budget of roughly ₹4 lakh, reduces power draw when a mobile phone’s screen is off and can be integrated into smartwatches, health‑monitoring wearables and hospital sensors. Anupama’s work, conducted under Professor Srihari Rao Patri, has passed laboratory tests and is currently in the R&D phase. The Indian government’s Ministry of Electronics and Information Technology funded its fabrication through the “Chips to Startup” (C2S) scheme, and a patent application is pending. The researcher is now seeking angel investors to move the design toward commercial production.
💡 Why It Matters
- · By cutting standby drain, the chip could unlock multi‑day operation for wearables, reshaping user expectations for portable health and IoT gadgets.
