Samsung First to Build 3D Stacked Transistor, Breaking Logic Chip Limits Vertically
AI-summarised brief · reviewed before publication
Samsung Electronics' Semiconductor R&D Center has successfully built a 3D Stacked Field Effect Transistor, a breakthrough in overcoming the physical limits of chip miniaturization. The achievement was presented at the VLSI Symposium 2026 and received the Best Paper award. This innovation adopts a vertical structure, stacking devices on top of one another, allowing for twice as many transistors to fit on a wafer of the same area. The research team reduced the gate pitch to 42 nanometers, breaking the previous industry record of 48 nm. This development marks the arrival of the era of three-dimensional logic semiconductors.
💡 Why It Matters
- · By stacking transistors vertically, Samsung overcomes the horizontal constraint on insulator thickness, allowing for denser transistor placement.
- · This breakthrough enables the creation of more complex and powerful logic semiconductors.