ACM Research Enhances Single-Wafer Hot SPM System with Sulfuric Acid Recycle Capability

semiconductor-digest.com Nov 11, 2026

ACM Research Enhances Single-Wafer Hot SPM System with Sulfuric Acid Recycle Capability

Curated by Shubham · TechCapsules · Nov 11, 2026

AI-summarised brief · reviewed before publication

ACM Research, Inc. unveiled an upgraded 170 °C Single‑Wafer Hot Sulfuric Peroxide Mixture (SPM) system that incorporates a sulfuric acid recycle feature. The new design uses a proprietary nozzle to eliminate crystalline deposits, allowing continuous operation without periodic DI water rinsing. Validation at a foundry across more than 50 process layers confirmed particle counts of 15 or fewer at 15 nm, outperforming mainstream solutions. The recycle capability achieves a 70 % acid recovery rate, saving roughly 400 tons of sulfuric acid per tool annually while maintaining stringent particle control.

💡 Why It Matters

· The system’s high‑efficiency acid reuse cuts chemical waste and operating costs, directly addressing the semiconductor industry’s growing demand for sustainable, low‑maintenance cleaning solutions.

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AMD Tunes Up CPUs For Agentic AI With “Venice” Epyc Processors

AMD announced its sixth‑generation “Venice” Epyc CPUs, built on the Zen‑6 microarchitecture, to meet the rising demands of agentic AI. The new chips enhance CPU orchestration of complex AI workflows, shifting the GPU‑to‑CPU ratio toward parity in data centers. AMD’s 46% market share and continued investment in Zen technology position it to compete with Intel and support the projected 43% annual growth of agentic AI. The release underscores a strategic pivot toward AI‑centric server workloads.

💡 The move signals a broader industry shift where CPUs, not GPUs, will drive the next wave of AI infrastructure, reshaping data‑center economics and competitive dynamics.

nextplatform.com · Nov 11

How The “Venice” Epycs Measure Up Against Prior AMD Server CPUs

AMD launched the sixth‑generation “Venice” EPYC processors, expanding its server portfolio to 31 SKUs that range from 8 to 256 cores, 130 W to 600 W, and $700 to $14,904 per 1,000‑unit tray. The line uses two distinct socket designs—SP7 for high‑density models and a smaller socket for lower‑tier parts—and pairs each with either a 12‑core or 32‑core compute chiplet (CCD) built on TSMC’s 2 nm process. Both CCD types retain identical cache hierarchies while differing in scheduler tuning, delivering higher core counts at lower clocks or fewer cores at higher clocks. The SP7 socket adds 16 DDR5 channels (up to 1.6 TB/s) and 96 PCIe 6.0 lanes, with a 6 nm I/O die. AMD claims a 20 % IPC gain over Zen 5, positioning Venice ahead of Intel’s current Xeon offerings and earlier ARM server options.

💡 By marrying ultra‑dense core configurations with a dramatically faster memory and I/O subsystem, Venice gives hyperscale operators a single‑chip path to scale workloads that were previously split across multiple sockets or heterogeneous architectures.

semiconductor-digest.com · Nov 11

Nordson Electronics Solutions Wins The 2026 Global Technology Award for the MARCH…

Nordson Electronics Solutions received the 2026 Global Technology Award in the Plasma Systems category for its MARCH ExoSPHERE plasma treatment system. The platform delivers plasma cleaning and surface activation to boost adhesion, yield and reliability in semiconductor packaging. Designed for PLP, the system supports panels up to 650 × 651 mm and accommodates wafers, carriers and warped panels via handlers. Its patented three‑axis symmetrical chamber provides uniform plasma exposure, while SMART Tune™ Management offers RF control that cuts tuning time and stabilizes power seconds. The technology enables underfilling, wicking, die‑attach and wire‑bond integrity, and reduces rework and part rejection. Judges evaluated the ExoSPHERE on innovation, throughput, quality, cost, impact, usability and maintainability at the SMTA International awards ceremony in Rosemont, Illinois.

💡 By guaranteeing consistent surface energy across large panels, ExoSPHERE removes a key bottleneck in high‑density AI and HPC chip packaging, directly lifting production yields.

techcrunch.com · Nov 10

Google broadens its AI hardware portfolio with two new specialized chips

Google unveiled two new tensor processing units—TPU 8tx and TPU 8i Max—expanding its eighth‑generation AI chip lineup. The TPU 8tx, co‑designed with AMD, adds hardware‑level security for confidential training and inference, allowing models to be refined on proprietary data without data movement, and includes a custom inferencing network for on‑the‑fly model distillation. The TPU 8i Max merges two TPU 8i inference chips into a single package, doubling memory, compute and bandwidth to support larger query workloads. Both chips aim to lessen Google Cloud’s reliance on external silicon, particularly Nvidia, as hyperscalers and AI labs develop their own processors. The announcements arrive amid heightened scrutiny of Nvidia’s leadership following CEO Jensen Huang’s personal controversy.

💡 By embedding security and scaling memory in its own silicon, Google can offer cloud customers private‑data AI services that competitors cannot match without third‑party chips.

semiconductor-digest.com · Nov 10

SEMI Foundation Launches Global Chip the Future Challenge

The SEMI Foundation has launched the Chip the Future Challenge™, a global competition for university students to propose research or innovative solutions in semiconductor design, manufacturing, AI hardware, advanced packaging, and emerging technologies. Participants may enter individually or in teams of up to five, submitting abstracts by November 14, 2026, with finalists announced December 1. Winners receive $10,000 in prizes and present to industry leaders. The event, backed by Micron Technology and Galatek, aims to connect fresh talent with real‑world industry challenges.

💡 By spotlighting student‑driven ideas, the challenge injects fresh perspectives into critical semiconductor problems, accelerating the pipeline of next‑generation solutions.

semiconductor-digest.com · Nov 10

Fraunhofer IPMS Highlights Semiconductor Technology Developments at SEMICON Europa

At SEMICON Europa 2026, Fraunhofer IPMS showcased advances in semiconductor integration, emphasizing energy‑efficient chiplets, memory, and photonic technologies. The institute highlighted its work on the APECS pilot line, part of the EU Chips Act, demonstrating 2.5D interposer integration and the first quasi‑monolithic integration (QMI) of chiplets into silicon wafers. These developments aim to combine logic, memory, and specialized functions into compact, high‑performance systems while reducing power consumption. The exhibition underscored Fraunhofer’s role in validating industry‑relevant processes for future chip architectures.

💡 By proving wafer‑level chiplet integration, Fraunhofer IPMS paves the way for scalable, low‑power systems that can meet the growing demand for high‑density, heterogeneous components in next‑generation electronics.