Fraunhofer IPMS Highlights Semiconductor Technology Developments at SEMICON Europa

semiconductor-digest.com Nov 10, 2026

Fraunhofer IPMS Highlights Semiconductor Technology Developments at SEMICON Europa

Curated by Shubham · TechCapsules · Nov 10, 2026

AI-summarised brief · reviewed before publication

At SEMICON Europa 2026, Fraunhofer IPMS showcased advances in semiconductor integration, emphasizing energy‑efficient chiplets, memory, and photonic technologies. The institute highlighted its work on the APECS pilot line, part of the EU Chips Act, demonstrating 2.5D interposer integration and the first quasi‑monolithic integration (QMI) of chiplets into silicon wafers. These developments aim to combine logic, memory, and specialized functions into compact, high‑performance systems while reducing power consumption. The exhibition underscored Fraunhofer’s role in validating industry‑relevant processes for future chip architectures.

💡 Why It Matters

· By proving wafer‑level chiplet integration, Fraunhofer IPMS paves the way for scalable, low‑power systems that can meet the growing demand for high‑density, heterogeneous components in next‑generation electronics.

Capsules Semiconductors

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SEMI Foundation Launches Global Chip the Future Challenge

The SEMI Foundation has launched the Chip the Future Challenge™, a global competition for university students to propose research or innovative solutions in semiconductor design, manufacturing, AI hardware, advanced packaging, and emerging technologies. Participants may enter individually or in teams of up to five, submitting abstracts by November 14, 2026, with finalists announced December 1. Winners receive $10,000 in prizes and present to industry leaders. The event, backed by Micron Technology and Galatek, aims to connect fresh talent with real‑world industry challenges.

💡 By spotlighting student‑driven ideas, the challenge injects fresh perspectives into critical semiconductor problems, accelerating the pipeline of next‑generation solutions.

semiconductor-digest.com · Nov 10

Infineon Processes Functional Power Devices on 300mm SiC Wafers

Infineon Technologies AG announced that its Villach, Austria fab has produced functional power devices on 300 mm silicon‑carbide (SiC) wafers, marking the first full‑scale semiconductor‑manufacturing run of this size for SiC. The breakthrough was achieved using existing silicon‑process equipment, allowing a 2.3‑fold increase in chip count per wafer compared with the traditional 200 mm format. CEO Jochen Hanebeck highlighted the milestone as a step toward industrial‑scale SiC production and a broader portfolio that includes silicon, gallium‑nitride and SiC. Infineon plans to coordinate 300 mm SiC ramp‑up with customers while continuing its 200 mm roadmap, and it has also validated a “Cold Split” wafer‑separation method that reduces material loss. The company will showcase the first processed 300 mm SiC wafer at electronica 2026 in Munich.

💡 By leveraging 300 mm wafers, Infineon can dramatically lower the cost per SiC device, accelerating the adoption of high‑efficiency power conversion in electric vehicles, renewable energy and AI data centers. This positions the firm to dominate the emerging wide‑bandgap market ahead of rivals still confined to smaller wafers.

semiconductor-digest.com · Nov 9

EV Group Advances Qubit Scaling Through Semiconductor Packaging Technology

EV Group (EVG) announced it will support quantum chip developers by applying its advanced packaging, heterogeneous integration and photonics manufacturing expertise to address scaling challenges in quantum computing. The company will showcase its process solutions—including fusion and hybrid bonding, oxide‑free bonding, digital and nano‑imprint lithography, and thin‑wafer processing—at SEMICON Europa in Munich (Nov. 10‑13). EVG’s technologies aim to meet the high‑density interconnection, material‑integration and precision‑alignment demands of diverse qubit architectures such as superconducting, photonic, spin, trapped‑ion, neutral‑atom and nitrogen‑vacancy diamond. Through its Heterogeneous Integration Competence Center™ and NILPhotonics® Competence Center, EVG intends to help customers develop and validate new chip designs and manufacturing flows that preserve qubit performance while enabling larger, fault‑tolerant systems for future commercial quantum computers worldwide applications today.

💡 By bridging disparate qubit technologies with proven semiconductor packaging, EVG removes a key bottleneck that has kept quantum processors small, accelerating the path to fault‑tolerant machines.

nextplatform.com · Nov 9

Google Rejiggers TPU Accelerators For Broader AI Inference Work

Google is preparing to roll out two re‑engineered TPU accelerators—Sunfish TPU 8t and Zebrafish TPU 8i—later in 2026, with broader deployment slated for Q1 2027 and a multi‑region ramp through 2028. The 8t, fabricated by Broadcom and TSMC, targets AI training, featuring a 3‑D torus interconnect linking 9,600 chips and delivering 121 exaflops at FP4 precision, plus 216 GB HBM3E per device. A derivative, the 8tx, swaps the torus for a lower‑latency “boardfly” fabric and replaces Google’s Axion ARM CPU with an AMD EPYC processor to optimise inference workloads. The 8i, shepherded by MediaTek, is intended for inference but its shipping status remains unclear. Both chips will augment Google Cloud’s offering after the earlier Ironwood v7p rollout, supporting Gemini 4 frontier models via a token‑based pricing scheme.

💡 By tailoring interconnects and CPUs for inference, Google can deliver faster response times for high‑throughput AI services, giving its cloud platform a performance edge over rivals.

semiconductor-digest.com · Nov 9

Semiconductor Companies Get Tough on AI Investment, but Measuring Returns Remains a…

HTEC’s latest research shows that semiconductor firms are ahead of most industries in AI adoption, with 48% labeling themselves as AI‑native or scaling AI versus 44% overall. Investment growth mirrors the broader market, as 78% report increased AI spending. The sector distinguishes itself by prioritizing strategic alignment and demanding formal ROI models before project approval—45% and 36% respectively. However, once AI initiatives launch, measurement fragments: 38% rely on case‑by‑case reporting and only 28% use enterprise dashboards, compared with 30% and 36% across other sectors. Respondents cite missing baselines, inconsistent KPIs, and unclear organizational goals as hurdles. Moreover, 83% say people and processes, not technology, limit AI value, while only about one‑fifth actively monitor cross‑functional adoption or provide comprehensive enablement for non‑technical staff.

💡 Without consistent value tracking, semiconductor firms risk misallocating AI spend, undermining the competitive edge their early adoption promises.

semiconductor-digest.com · Nov 7

Diamond Foundry Announces First-Ever D200mm Single-Crystal Diamond

Diamond Foundry Inc. announced the creation of the first 200‑millimeter single‑crystal diamond, a breakthrough that enables diamond to be produced at semiconductor‑relevant wafer scale. The milestone, presented by CEO Martin Roscheisen during a keynote at CarbonSemi 2026 in Ningbo, China, required advances in crystal growth, plasma physics, reactor design, and process control. The achievement marks a pivotal step toward using diamond’s superior thermal conductivity and mechanical strength in high‑power electronics, AI processors, and quantum devices.

💡 By overcoming the size barrier, this development unlocks diamond’s potential to dissipate heat in next‑generation chips, enabling higher power densities and more reliable, compact computing systems.