Aeluma Orders AIXTRON MOCVD System to Expand Photonics Manufacturing

semiconductor-digest.com Nov 12, 2026

Aeluma Orders AIXTRON MOCVD System to Expand Photonics Manufacturing

Curated by Shubham · TechCapsules · Nov 12, 2026

AI-summarised brief · reviewed before publication

Aeluma, Inc. has signed an agreement to purchase an AIXTRON G10‑AsP metalorganic chemical vapor deposition (MOCVD) system, enabling the company to expand production of its non‑indium‑phosphide photonics platform. The new tool supports 150 mm and 200 mm wafers and is tailored to Aeluma’s proprietary processes, allowing integration of gallium arsenide or silicon substrates with compound semiconductors. The acquisition aims to meet rising demand for high‑speed photonic components in AI data communications and to scale manufacturing without relying on InP substrates.

💡 Why It Matters

· The move positions Aeluma to capitalize on the growing AI‑driven photonics market, offering a scalable, cost‑effective alternative to traditional InP‑based solutions.

Capsules Semiconductors

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Almere, Flevoland and Q.ANT Team Up for Computing with Light

German deep‑tech firm Q.ANT, Dutch high‑tech hub High Tech Almere, and regional body Horizon Flevoland signed a Memorandum of Understanding at SEMICON Europa in Munich. The partnership aims to develop, validate, and scale photonic computing solutions in Almere and Flevoland. Q.ANT’s light‑based processors promise orders‑of‑magnitude energy efficiency and lower cost for AI workloads. The collaboration will pilot applications in digital infrastructure, logistics, healthcare, and public sector, while fostering talent and ecosystem growth in the Dutch‑German corridor.

💡 By integrating photonic processors into existing data‑centre stacks, the alliance could dramatically reduce AI’s energy footprint, addressing a critical barrier to widespread adoption. The pilots will test real‑world use cases, potentially accelerating commercial deployment of ultra‑efficient AI hardware.

semiconductor-digest.com · Nov 13

ViTrox Reports Nearly 200 AI-Powered X-Ray Inspection Systems Deployed

ViTrox is showcasing its AI‑driven 3D AOI, 3D AXI and manufacturing‑intelligence portfolio at SEMICON Europa 2026 in Munich from 10‑13 November. The company highlights how its solutions help European manufacturers tackle increasingly minute and buried defects in advanced packaging, heterogeneous integration and high‑density SMT lines. Key products include the V510Ai ST front‑end AOI for large PCBs, the V510Ai Vision Pro with SWIR imaging for inner‑die cracks, and the award‑winning V810Ai QX1 X‑ray system offering 2 µm resolution and ±50° tomography. ViTrox reports that nearly 200 V810Ai QX1 units have been installed within the past year by major AI‑server makers, underscoring rapid market adoption. All systems integrate with the V‑ONE Manufacturing Intelligence platform, providing real‑time imaging, auto‑ticketing and root‑cause analytics to enable closed‑loop quality control across the factory.

💡 The deployment surge proves AI‑enabled X‑ray inspection is becoming a production‑line standard for detecting sub‑micron defects at speed, reshaping quality assurance in Europe’s high‑tech manufacturing.

semiconductor-digest.com · Nov 13

Teledyne Vision Solutions Demonstrates Single-Pass 300mm Wafer Inspection

Teledyne Vision Solutions is showcasing its latest semiconductor inspection tools at SEMICON Europa 2026 in Munich. At Hall C2, Stand 136, the company will demonstrate the Linea ML 32K line‑scan camera, which can image a 300 mm wafer in a single pass at 10 µm resolution. The camera, the first true 32K line‑scan device, offers 32 K pixels, 2.5 µm pixel size and speeds up to 150 kHz, plus advanced modes such as multiline, HDR and TDI to boost defect detection and simplify system integration. Teledyne will also present the Z3 3D Measurement System, delivering up to 1.25 µm spatial resolution, 35 nm height repeatability and two‑second per‑wafer throughput. The Z3 combines high‑resolution 3D and 2D imaging for metrology of micro‑BGA, bumps, pillars, TGV/TSV, wafer bonding, flatness and defect analysis, supporting AI‑hardware production lines.

💡 The ability to inspect a full 300 mm wafer in one pass at micron‑scale detail could dramatically cut cycle time and improve yield for next‑generation chip manufacturers.

semiconductor-digest.com · Nov 13

Texas Tech Receives $19 Million Grant to Further Semiconductor Innovation

Texas Tech University’s Edward E. Whitacre Jr. College of Engineering received a Texas Semiconductor Innovation Fund award exceeding $19 million to build a next‑generation high‑performance computing cluster in Lubbock. The cluster will integrate Nvidia GPUs, AI, and advanced simulation data to accelerate semiconductor device and material development, particularly wide/ultrawide bandgap technologies for harsh environments. The grant follows prior TSIF awards that funded a new clean room and bandgap research, positioning Texas Tech as a pioneer in AI‑driven semiconductor innovation.

💡 The investment equips Texas Tech with cutting‑edge computational resources that can dramatically shorten semiconductor development cycles, directly supporting the state’s expanding high‑tech workforce and positioning the university as a leader in AI‑enhanced materials research.

semiconductor-digest.com · Nov 12

imec and ASRA Release Joint Architectural Requirements for Interoperable Automotive Chiplets

Imec and Japan’s Advanced SoC Research for Automotive (ASRA) released the Automotive Chiplet Interoperability Requirement (ACIR) at the Autonomous Edge Chiplet Forum. ACIR establishes a shared set of architectural specifications—covering error handling, boot sequencing, power management, functional safety, and die‑to‑die connectivity—to enable cross‑vendor integration of automotive chiplets. The document aims to accelerate adoption of chiplet architectures by providing an open reference for OEMs, Tier‑1 suppliers, and semiconductor vendors, fostering a global, interoperable ecosystem.

💡 By standardizing how chiplets communicate and manage faults, ACIR removes a key barrier to multi‑vendor system integration, allowing automotive manufacturers to mix and match components without redesigning interfaces. This paves the way for faster, more cost‑effective deployment of high‑performance computing solutions in next‑generation vehicles.

semiconductor-digest.com · Nov 12

imec Advances Silicon Interposer Platform for European Chiplet Development

At SEMICON Europa 2026, imec unveiled baseline flows for its silicon interposer platform within the NanoIC pilot line, marking a key advance in European chiplet packaging. The platform details architecture, manufacturing steps, and design features such as through‑silicon vias, multiple metal layers, and 20 µm microbump pitch, enabling high‑density interconnects for AI accelerators and GPUs. A dedicated process design kit (PDK) will launch early 2027, allowing universities, start‑ups, and fabless firms to simulate and prototype the technology in standard EDA tools.

💡 By providing a ready‑to‑use silicon interposer PDK, imec equips designers with the tools to rapidly prototype high‑bandwidth, low‑energy chiplet systems, accelerating the deployment of next‑generation AI and compute platforms in Europe.