STMicroelectronics Adds MasterGaN7 Devices to Integrated High-Efficiency Power Family

semiconductor-digest.com Oct 22, 2026

STMicroelectronics Adds MasterGaN7 Devices to Integrated High-Efficiency Power Family

Curated by Shubham · TechCapsules · Oct 22, 2026

AI-summarised brief · reviewed before publication

STMicroelectronics has expanded its MasterGaN integrated transistor/driver portfolio with the MasterGaN7 series, featuring 650 V enhancement‑mode GaN transistors rated for 6 A. The half‑bridge devices combine two high‑voltage GaN switches with a gate driver in a QFN package that shares pinout with earlier MasterGaN parts, enabling designers to improve efficiency and power density in power adapters, chargers, industrial lighting and solar micro‑inverters. Integrated low‑drop‑out regulators stabilize gate‑drive voltage, while a pin‑driven shut‑down mode and fast wake‑up reduce no‑load consumption. With a 45 ns propagation delay, 2 MHz switching capability, bootstrap diode and protection, the parts require components, lowering BOM cost and footprint. Production units are now in a 9 mm × 9 mm QFN, priced from $3.83 per thousand, and an EVLMG7 evaluation board is offered for prototyping.

💡 Why It Matters

· The ultra‑compact, high‑frequency GaN solution lets OEMs slash board size and component count, accelerating time‑to‑market for next‑gen power converters.

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SEMI Forecasts 11.8% Growth in Silicon Wafer Shipments in 2026, With Record…

SEMI’s latest silicon wafer shipment forecast projects an 11.8% rise in 2026, reaching 14,420 million square inches (MSI). Shipments are expected to climb to 17,034 MSI by 2029, marking consecutive record highs. Growth is driven by robust AI demand, which fuels advanced epitaxial wafers for cutting‑edge logic and polished wafers for memory, including HBM, server DRAM, and enterprise NAND flash. Recovering mature‑node utilization and reduced inventory adjustments also support the uptick. The forecast reflects input from the Silicon Manufacturers Group.

💡 The surge underscores AI’s expanding hardware footprint, positioning silicon wafers as a critical bottleneck that could shape supply chain dynamics and chip innovation in the coming years.

semiconductor-digest.com · Oct 22

NVIDIA and Supply Chain Partners Expand Capacity to Accelerate AI Infrastructure Buildout

NVIDIA announced a coordinated expansion of its global manufacturing network with partners Amkor Technology, IBIDEN, King Yuan Electronics, Samsung Electro‑Mechanics, Siliconware Precision Industries and Unimicron. The plan adds substrate capacity by 2.5 times over three years, triples interposer wafer output, doubles testing capability and multiplies optical‑engine production, with key milestones reaching full capacity between 2027 and 2028. NVIDIA is providing multibillion‑dollar reservation advances to secure space at IBIDEN’s Ono plant, to fund Samsung’s upgrades in Sejong and Busan, and to support KYEC’s U.S. testing facilities. CEO Jensen Huang called the effort the “largest infrastructure buildout in human history,” aimed at removing capacity constraints as demand for AI supercomputing systems soars. The expanded supply chain will improve redundancy and lower times worldwide.

💡 Securing massive production capacity now lets NVIDIA outpace rivals and lock in supply for the AI hardware surge, turning a bottleneck into a strategic edge.

semiconductor-digest.com · Oct 22

Navitas Unveils Next-Generation Ultra-High-Voltage SiC Power Module

Navitas Semiconductor announced a new ultra‑high‑voltage SiC power module family, the G4H08MT23GB4, rated at 2300 V and built on the SiCPAK™ form factor. The full‑bridge devices achieve a class‑leading on‑resistance of 8 mΩ thanks to the fourth‑generation GeneSiC™ Trench‑Assisted Planar™ architecture. Enhanced thermal management comes from an aluminum‑nitride active‑metal‑braze substrate, epoxy‑resin potting and optional pre‑applied thermal interface material, while press‑fit pins double current capacity. Navitas qualified the modules to its AEC‑Plus reliability benchmark, extending high‑temperature, high‑voltage and power‑cycling tests beyond JEDEC standards. Target applications include solid‑state transformers for AI data‑center racks, grid‑scale battery storage, solar inverters and megawatt EV chargers, positioning the parts as a core building block for emerging medium‑voltage power architectures. The launch expands Navitas’ 2300 V and 3300 V SiC portfolio.

💡 By delivering the lowest on‑resistance in a SiCPAK package, the module lets designers shrink solid‑state transformers, cutting system size and cooling needs for AI‑driven data centers.

semiconductor-digest.com · Oct 22

Why “Faster Chips” Don’t Feel Faster

Faraj Aalaei, founder and CEO of Cognichip, argues that modern chips are technically fast but fail to deliver perceived speed because the industry prioritizes raw performance over system‑level efficiency. He explains that long design cycles and added flexibility create mismatches across memory, software, and networks, causing chips to idle and drain energy. Aalaei calls for new tools that evaluate entire systems early, aiming to reduce energy waste, improve competitiveness, and restore the user experience.

💡 By shifting focus from isolated performance to holistic system design, the industry can unlock real-world speed gains and curb escalating power consumption.

semiconductor-digest.com · Oct 22

The Five Factors Defining the Next Generation of AI Inference Chips

Ankur Saxena of TDK Ventures explains that AI inference chips are evolving from raw compute benchmarks to a multi‑factor design framework. He identifies five critical dimensions: performance beyond TOPS, cost per inference, power consumption, privacy for edge deployments, and programmability via compilers and software. Saxena cites Groq, Sagence AI, EdgeCortix, and Mixx Technologies as exemplars of diverse approaches. He argues that no single architecture will dominate, as data centers, interactive apps, industrial systems, robots, and defense each demand distinct optimizations.

💡 The shift to a holistic evaluation of inference chips signals a move toward tailored solutions that balance speed, cost, and security, reshaping how AI is embedded across industries.

semiconductor-digest.com · Oct 22

Stacking Up: Inside the Industry’s Race to Build CFET Transistors

The semiconductor industry’s next transistor architecture, the complementary FET (CFET), stacks n‑type and p‑type devices vertically to halve logic footprints. Intel, TSMC, Samsung, and IBM Research have fabricated working silicon, showcasing CFET inverters at 45 nm gate pitch with backside PowerVia and Samsung’s three‑nanosheet channel devices at 42 nm. While most groups use monolithic integration, IBM’s Nanostack adopts a sequential bonding approach to avoid thermal limits. Persistent process challenges include contacting buried transistors and etch selectivity. CFET production is projected for the early 2030s, marking a pivotal shift after gate‑all‑around technology.

💡 The successful demonstration of CFETs signals a new era of density and power efficiency, potentially redefining design rules for future chips. It demonstrates that industry leaders are moving beyond gate‑all‑around, opening pathways for next‑generation logic performance.