From Fluid Handling to Dose Control: How Valve Technology Evolved from Process Component to Dose-Control Enabler

semiconductor-digest.com Oct 26, 2026

From Fluid Handling to Dose Control: How Valve Technology Evolved from Process Component to Dose-Control Enabler

Curated by Shubham · TechCapsules · Oct 26, 2026

AI-summarised brief · reviewed before publication

Jeff DeWitt, lead applications engineer at Swagelok, outlines three evolutionary phases of semiconductor valve technology driven by the tightening demands of atomic‑layer processes. In the “purity” era, valves were evaluated mainly on leak tightness, diaphragm integrity, cycle life and cleanliness. The shift to high‑volume atomic‑layer deposition (ALD) ushered in the “performance” era, where flow‑path geometry, conductance, purgeability and thermal stability became critical to maintain throughput and yield across wafers. The current “precision” era focuses on dose control—the exact number of moles delivered during millisecond‑scale valve‑open pulses in advanced ALD and atomic‑layer etch. At these time scales, minute variations in actuation and conductance drift dominate, making dose regulation a system‑level outcome rather than a function of any single valve.

💡 Why It Matters

· Precise mole‑by‑mole dosing is now the bottleneck for scaling 3‑D semiconductor architectures, directly linking valve engineering to device performance and yield.

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Taking a Holistic Approach to Co-Packaged Optics Manufacturing

Thomas Achleitner of EV Group explains that scaling AI systems requires efficient data movement, which co‑packaged optics (CPO) can provide by integrating photonic and electronic components in a single package. Achleitner stresses that high‑volume CPO production demands expertise in bonding, nanoimprint lithography, and heterogeneous integration rather than a single technological breakthrough. Techniques such as hybrid bonding, die‑to‑wafer fusion, oxide‑free room‑temperature bonding, and wafer‑level nanoimprint lithography enable low‑parasitic integration, selective laser placement, thermal management, and mass‑produced optical interfaces. The article highlights how these methods will become increasingly intertwined as the industry advances toward optical I/O chiplets and 3D photonic‑electronic integration.

💡 The convergence of diverse materials and bonding techniques is essential for delivering the high‑speed, low‑latency data pathways that future AI workloads demand.

semiconductor-digest.com · Oct 26

The High-Tech Workforce Has Changed, and Employers Need to Change With It

New semiconductor fabs across the U.S. face a quiet bottleneck: sourcing skilled engineers, tradespeople, and cleanroom staff. Tamara Ellestad, CEO of VELO, notes staffing demand has surged, with candidates juggling multiple tool‑installation calls daily. Workers now seek competitive pay, flexibility, travel, and growth, favoring 12‑ to 24‑month projects over permanent moves. VELO reports a 60% drop in qualified candidate shelf life due to slow feedback. Ellestad urges early workforce planning and flexible hiring models to secure talent.

💡 Rapid talent turnover threatens project timelines and costs, making proactive pipeline building essential for sustaining U.S. fab expansion.

semiconductor-digest.com · Oct 24

Gigaphoton Takes Its Lightsources Beyond the Scanner

Gigaphoton, a Komatsu subsidiary that has supplied over 2,500 KrF and ArF excimer lasers to DUV scanners for 26 years, announced at SEMICON West that it is expanding beyond lithography into four new fab applications. The company unveiled the G300K, a 248 nm KrF laser delivering 300 W at up to 4 kHz, designed for ultra‑fine ablation of advanced‑packaging substrates. Using mask‑projection optics, the system can drill multiple vias simultaneously, achieving diameters as small as 3 µm with near‑vertical sidewalls and minimal heat‑affected zone, far surpassing CO₂ and 355 nm UV lasers. Gigaphoton also outlined efforts on a compact EUV source, EUV‑based mask inspection, gas‑recycling for neon supply security, and pulsed‑laser deposition for superconducting wire, positioning its short‑wavelength technology for heterogeneous integration and future chiplet interconnects.

💡 By delivering sub‑10 µm vias in a single exposure, Gigaphoton’s excimer laser could eliminate costly multi‑step lithography for chiplet packaging, accelerating the shift to dense heterogeneous integration.

semiconductor-digest.com · Oct 24

Department of Commerce Announces Letters of Intent With 4 Companies for $389…

The U.S. Department of Commerce signed letters of intent to award up to $389 million in CHIPS‑Act research grants to four firms for power‑electronics R&D. Helion will receive up to $175 million to develop high‑voltage semiconductors and modules for pulsed‑power fusion generators. Commonwealth Fusion Systems is slated for up to $85 million to create RF plasma‑heating semiconductors, embedded diagnostics electronics and radiation‑hard components. Vertical Semiconductor will get up to $73 million to advance vertical gallium‑nitride power devices and demonstrate a 2.5 MW AI data‑center rack. Sibelco will obtain up to $56 million to produce ultra‑high‑purity quartz for crystal growth and other semiconductor hardware. The awards aim to boost domestic supply chains, reduce foreign dependence, and secure high‑paying jobs, with the Commerce Department taking a minority equity stake in each company.

💡 By funding core power‑semiconductor and material breakthroughs, the grants directly strengthen U.S. energy‑grid resilience and the emerging fusion‑energy sector, giving America a strategic edge in critical technology supply chains.

semiconductor-digest.com · Oct 24

Atomera, IQE Partner on RF GaN-on-Silicon for Volume Markets

Atomera and IQE plc have signed a Joint Development Agreement to demonstrate gallium‑nitride (GaN) epitaxy on Atomera’s Mears Silicon Technology (MST)‑enabled silicon wafers for radio‑frequency (RF) applications. The partnership combines Atomera’s quantum‑engineered silicon substrate, which promises higher transistor performance and lower cost, with IQE’s expertise in compound‑semiconductor epitaxy. Teams will co‑engineer a multi‑layer GaN‑on‑silicon structure aimed at delivering best‑in‑class linearity and loss for high‑volume RF markets, with the intent to produce test wafers for foundries, IDMs and fabless customers. The JDA envisions a multi‑cycle development process and leaves open the possibility of extending the technology to power‑electronics GaN use cases, potentially accelerating MST‑based wafer availability for mainstream markets.

💡 By marrying low‑cost silicon with high‑performance GaN, the collaboration could unlock affordable, mass‑produced RF components that were previously limited to expensive substrates.

semiconductor-digest.com · Oct 22

SEMI Forecasts 11.8% Growth in Silicon Wafer Shipments in 2026, With Record…

SEMI’s latest silicon wafer shipment forecast projects an 11.8% rise in 2026, reaching 14,420 million square inches (MSI). Shipments are expected to climb to 17,034 MSI by 2029, marking consecutive record highs. Growth is driven by robust AI demand, which fuels advanced epitaxial wafers for cutting‑edge logic and polished wafers for memory, including HBM, server DRAM, and enterprise NAND flash. Recovering mature‑node utilization and reduced inventory adjustments also support the uptick. The forecast reflects input from the Silicon Manufacturers Group.

💡 The surge underscores AI’s expanding hardware footprint, positioning silicon wafers as a critical bottleneck that could shape supply chain dynamics and chip innovation in the coming years.